The ’HC138 devices are designed to be used in high-performance memory-decoding or data

routing    applications   requiring very short

propagation  delay  times.  In  high-performance

memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit,

the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-mA Max ICC

Typical tpd = 15 ns

±4-mA Output Drive at 5 V

Low Input Current of 1 mA Max

Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.

A 24-line decoder can be implemented without external inverters, and a 32-line decoder req

uires only one inverter. An enable input can be used as a data input for demultiplexing applications.

SN74HC138N is a 3-line to 8-line data selector/multiplexer. It can select one of eight digital inputs and transfer it to a digital output. This device can be used in a variety of products, such as electronic computers, control systems, communication systems, and others. Some applications include:

1 Digital signal selection and allocation

2 Data selection and allocation

3 Data conversion

4 Signal source selection

The specific use will depend on the system design.

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